As dimensions of components decrease in integrated circuits, the resistance of connections in metal layers of an integrated circuit correspondingly increases resulting in a significant IVD/DVD for large drive-strength cells. An aspect of particular concern relates to distribution of a global clock in which large drive-strength standard cells are used for efficient clock-signal transport over large distances.
If the power and ground connections of the large clock cells are to the same metal power mesh as the surrounding standard cell logic gates, any IVD/DVD induced in the power mesh by the clock driver may be experienced by the surrounding logic gates, and vice versa.